The present invention relates to a clock generation circuit, and more particularly, to a clock generation circuit configured to generate a frequency-divided clock using a delay locked loop (DLL) circuit.
Various clock generation circuits are used to supply a clock signal with a predetermined frequency to a system. A high clock frequency is difficult to be directly realized by a clock generation circuit. Therefore, a clock generation circuit that multiplies a frequency of a low frequency clock to generate a high frequency clock is employed to generate a clock having the predetermined frequency. In general, the clock generation circuit including a delay locked loop (DLL) circuit combined with an edge combination unit is being used to multiply the frequency of the clock.
FIG. 1 illustrates a conventional clock generation circuit.
Referring to FIG. 1, the conventional clock generation circuit includes a phase control unit 101, a voltage control delay unit 107, and an edge combination unit 109. The phase control unit 101 includes a phase comparison unit 103 and a delay control unit 105.
The phase comparison unit 103 compares the phase of a delay clock CLKD_M fed back from the voltage control delay unit 107 with the phase of a reference clock CLK, to thereby output a comparison signal CMP, which contains information on the phase difference between the reference clock CLK and the delay clock CLKD_M, to the delay control unit 105.
The delay control unit 105 outputs a delay signal VCTRL, which controls a reference delay amount (see DD in FIG. 2), to the voltage control delay unit 107 in response to the comparison signal CMP outputted from the phase comparison unit 103.
The voltage control delay unit 107 includes a plurality of delay units, e.g., M number of delay units, which are connected in series. The voltage control delay unit 107 delays the reference clock CLK and the output signal of each delay unit by the reference delay amount DD in response to the delay control signal VCTRL generated by the delay control unit 105, thereby outputting first to Mth delay clocks CLKD_1 to CLKD_M. The first to Mth delay clocks CLKD_1 to CLKD_M outputted from the delay control unit 105 also are respectively inputted to the edge combination unit 109. Therefore, the reference clock CLK is delayed by the reference delay amount DD whenever it passes through the delay units of the voltage control delay unit 107. A total delay amount of the voltage control delay unit 107 corresponds to L cycles of the reference clock CLK, that is, M×DD=L×tCLK (where M and L are natural numbers), where tCLK denotes one cycle of the reference clock CLK. Accordingly, the Mth delay clock CLKD_M outputted from the last delay unit is in phase with the reference clock CLK.
The first to Mth delay clocks CLKD_1 to CLKD_M are inputted to the edge combination unit 109. The edge combination unit 109 generates a clock toggling in response to the rising or falling edge of each of the first to Mth delay clocks CLKD_1 to CLKD_M, thereby multiplying a frequency of the reference clock CLK. Operation of the edge combination unit 109 will be more fully described with reference to FIG. 2.
FIG. 2 is a timing diagram illustrating the operation of the edge combination unit 109. To facilitate understanding, description will be made on one exemplary case where the voltage control delay unit 107 generates first to fourth delay clocks CLKD_1 to CLKD_4, and the total delay amount given by the voltage control delay unit 107 is one cycle (tCLK) of the reference clock CLK, i.e., L=1.
The fourth delay clock CLKD_4 is in phase with the reference clock CLK, and the reference delay amount DD of each delay unit of the voltage control delay unit 107 is equal to a quarter of a period of the reference clock CLK.
FIG. 2 exemplarily illustrates that the edge combination unit 109 generates a clock toggling in response to rising edges of the first to fourth delay clocks CLKD_1 to CLKD_4.
The output clock CLK_OUT of the edge combination unit 109 is activated to a logic high level in synchronization with the rising edges of the first and third delay clocks CLKD_1 and CLKD_3 and is deactivated to a logic low level in synchronization with the second and fourth delay clocks CLKD_2 and CLKD_4. The period of the output clock CLK_OUT of the edge combination unit 109 is half of the period of the reference clock CLK (i.e. 2DD), and thus the frequency of the output clock CLK_OUT of the edge combination unit 109 is two times the frequency of the reference clock CLK. Thus, the edge combination unit 109 multiplies the frequency of the reference clock CLK of the edge combination unit 109 by two. As the number of delay clocks becomes larger, the edge combination unit 109 can multiply the frequency of the reference clock CLK by a higher multiplication ratio.
Meanwhile, a phase mixing unit (not shown in FIG. 1) may be used besides the edge combination unit 109, and the phase mixing unit multiplies the frequency of an input clock by mixing phases of a plurality of delay clocks.
However, the conventional clock generation circuit is disadvantageous in that the edge combination unit 109 and the phase mixing unit have such complicated circuit configurations that a malfunction may occur during frequency multiplication. Moreover, in a conventional clock generation circuit, the layout area required for the clock generation circuit should be great due to the circuit configurations of the edge combination unit 109 and the phase mixing unit.